Hasso-Plattner-Institut Potsdam Operating Systems and Middleware Group at HPI University of Potsdam, Germany
Operating Systems and Middleware Group at HPI

Seminar: Resource Management on Power

Winter 2016/17

Prof. Dr. Andreas Polze

Felix Eberhardt, M.Sc.
Max Plauth, M.Sc.
Frank Feinbube, M.Sc.

Organization

Extent: 2 semester hours (3 graded credit points)

Dates: Wednesday, 11.00 - 12.30, HS3

The seminar focusses on conducting and evaluating experiments on IBM Power Hardware. Participants are required to read fundamental scientific publications and technical documentation on mechanisms of the IBM Power and IBM OpenPower Hardware as well as Software Tools and Operating Systems. Experiments should be planned, evaluated and presented to the fellow students. The Participants are required to hand in a written report of the results.
  • Each participant is expected to plan, conduct and evaluate an experiment.
  • Each participant is expected to give a 30-45 minute presentation on their experiment and the background topic.
  • Presentation slides should be discussed with a supervisor one week prior to the presentation date.
  • Each participant is required to hand in a written report of the results. 6 - 8 Pages with the following Template (...). Deadline: 01.04.17
  • At the end of the seminar, we plan to assemble a technical report about your seminar topics.

Topics

  1. Simultaneous Multithreading

    Papers:

    • Advanced features in IBM POWER8 systems, Sinharoy et al., link
    • IBM POWER8 processor core microarchitecture, Sinharoy et al., link more details
    • Performance Optimization and Tuning Techniques for IBM Power Systems Processors Including IBM POWER8; Bergner et al., link

    Possible Topics:
    For each: How can this be caused? What is the overhead, worst case, best case?

    • SMT Modes and automatic switching / rebalancing
    • SMT Priorities: Priority boosting and problem-state programs
    • TurboCore: configure frequency, voltage and cache resources per core. Can the voltage be reduced until the core is unstable?

  2. Transactional Memory

    Papers:

    • The cache and memory subsystem of the IBM POWER8 processor, Starke et al., link
    • Transactional memory support in the IBM POWER8 processor, Le et al., link
    • Quantitative comparison of hardware transactional memory for Blue Gene/Q, zEnterprise EC12, Intel Core, and POWER8, Nakaike et al., link
    • Robust Architectural Support for Transactional Memory in the Power Architecture, Cain et al., link
    • Solutions to IBM POWER8 verification challenges, Schubert et al., link
    • Verification of transactional memory in POWER8, Adir et al., link
    • Transactional Memory Today, Scott, link
    • Reduced Hardware NOrec: A Safe and Scalable Hybrid Transactional Memory, Matveev et al., link
    • Towards Transactional Memory for OpenMP, Wong et al., link
    • Thread-level speculation on off-the-shelf hardware transactional memory, Odaira et al., link
    • Eliminating global interpreter locks in ruby through hardware transactional memory, Odaira et al., link

    Possible Topics:

    • Hello World
    • Suspend region and breadcrumb debugging
    • Worst Case discussion: No guarantee of forward progress + Transactions may be nested (62 times in POWER8)
    • Emulated instructions

  3. Monitoring/Profiling Tools for IBM Power
  4. Hardware Virtualization Techniques in IBM Power
  5. PowerVM/PowerKVM API and Performance Comparison
  6. PowerVP: Monitoring on System Level
    Experimente:
    • Dynamic Platform Optimizer laufen lassen, vorher/nachher, wie kann ein Worst-Case erzeugt werden?
    • Daten- und Thread- Platzierung mit Libnuma
    • Capacity Planning: Entitlement vs. real usage of resources
    • Resourcen-Vergabe in Shared Pools
    • Performance-Daten analytisch auswerten
    Related Work:
    • PowerVM Hypercalls
    • PowerVM Hardware -> Linux Device Trees
    • Capacity Planning
    • https://www.youtube.com/watch?v=xL9E7-gVw4Q
    • https://www.youtube.com/watch?v=QiNcoz3P638
  7. RAS Features of IBM Power Systems
  8. Cache Structure, Coherency Protocol and Data Prefetchers
  9. Coherent Accelerator Processor Interface
  10. Accelerator Facilities in IBM Power/OpenPower
Assignments: Google Docs

Presentation Dates

According to your prioritized lists of topics the seminar schedule is as follows:

<-- -->
Date Topic Presenter
19.10.2016 Introduction Andreas Polze, Felix Eberhardt, Max Plauth
02.11.2016 Topic Assignment *
16.11.2016 Topic discussion *
14.12.2016 Experiment discussion Felix Wolff, Robert Schmid, Konstantin Harmuth
18.01.2017 Presentations tba
25.01.2017 Presentations tba
01.02.2017 Presentations??? Felix Wolff
08.02.2017 - -